Manufacture of an existing Thin Film Transistor (TFT) LCD involves an array process phase where an array substrate is formed on which there are several separated TFT pixel array circuits. The pixel array is required to be tested after being formed by deposit. A specific testing method is to deposit a testing circuit for inputting a testing signal together with the pixel array onto a glass substrate, with the testing circuit being located peripherally to each pixel area. Having completed the test, the testing circuit is removed in a cutting procedure of a Cell process.
FIG. 1 shows a prior art testing circuit in which gate lines 1 and data lines 2 are leaded from peripheral of pixel areas, among which odd lines and even lines are leaded, respectively, to connect with a testing signal terminal of the testing circuit via a testing bus. In particular, the odd lines of gate lines 1 are connected with a gate testing odd terminal GO (Gate Odd) via a gate testing odd bus 11; the even lines of gate lines 1 are connected with a gate testing even terminal GE (Gate Even) via a gate testing even bus 12; the odd lines of data lines 2 are connected with a data testing odd terminal DO (Data Odd) via a data testing odd bus 21; and the even lines of data lines 2 are connected with a data testing even terminal DE (Data Even) via a data testing even buses 22. In the testing circuit, in addition to the above four testing signal terminals, a common electrode terminal Vcom (Common) is included for testing a common electrode 3.
During testing, a device obtains input signals by connecting a probe pin with respective testing signal terminals integrated on the glass substrate, while a modulator move transversely (left-right) over the glass substrate by 15 um to receive surface electric fields of pixel areas thereby deciding whether each pixel functions normally, so as to implement the test.
Defects of the prior art include: since resistances of the lead lines of the testing circuit integrated on the glass substrate are great, when the above testing circuit is applied to a large size LCD, an obvious attenuation occurs in the testing signals in a direction from the testing signal terminals along the bus due to voltage dividing effect and resistance-capacitance delay (RC Delay) effect of the resistance of the lead lines, such that testing signals are too low in some parts of the display screen. Therefore, the voltages of the testing signals on the entire display screen are non-uniform and thus the test result is degraded. Especially, the non-uniformity in the voltages of the testing signals makes more contribution to this situation. Below, taking the even lines of the data lines 2 as an example, the detailed reasons of generating the voltage dividing effect and the RC delay effect are explained in connection with FIG. 2. The principle for the problem incurred by the gate lines 1 and the odd lines of the data lines 2 is similar and thus omitted.
1. The Voltage Dividing Effect
A certain leaking current exists between the data testing even bus 22 and the common electrode 3 as shown by dash lines in FIG. 2. Although this leak current is weak, in case where number of the signal lines 2 is relative great, length of the data testing even bus 22 increases significantly and the resistance R thereof increases accordingly. Thus a part of voltage is consumed over the data testing even bus 22, such that a signal voltage measured on a data line 2 far away from the data testing even terminal DE must be relatively low, which causes attenuation in the signals of this area and non-uniformity in the voltages of the testing signals.
As shown in FIG. 2, provided number of data lines 2 is n, a voltage drop between the leftmost data line and the rightmost data line may be calculated by the following formulaΔV=R*i*n+R*i*(n−1)+R*i*(n−2)+ . . . +R*i Where ΔV represents the voltage drop, i stands for the leaking current, and R denotes the resistance value between signal connecting terminals on the data testing even bus 22 as to every two adjacent data lines 2. It can be seen from the above formula, the more the resistances Rs are, the greater the voltage drop ΔV is and the more non-uniform the signal voltages are.
2. The RC Delay Effect
As shown in FIG. 2, after passing through the pixel area, the data line 2 connect at an end thereof to the common electrode in a form of a static-electric-proof ring, and can be deemed as open at this time. Since internal structures of respective data lines 2 in the pixel areas are same, difference among the RC delays depends totally on difference among peripheral testing circuits. According to calculation formula for circuit impedance, in case where capacitance and induction are same, the RC delays of respective signal lines increase as the resistance in the circuit increases. The resistance increases gradually from the input terminal to another terminal of the data testing even bus 22, leading to an increase in the RC delay accordingly. Thus, the signals of the data lines far away from the data testing even terminal DE arrive by a delay so that TFT devices can not be charged fully in a limited scanning period, resulting in attenuation in the signals.
In attenuation process of the testing signals, although it has not been verified that which one of the voltage dividing effect and the RC delay effect is dominant, a primary reason causing attenuation in the signals must be one of them which are desiderated to be solved.
Besides, to overcome the above problems, as shown in FIG. 3, in the prior art, a solution of wiring at both ends of the glass substrate to add signals from the both sides may be employed. As shown in FIG. 4, this solution may reduce errors to a certain degree, but still has defects as follows
1. Modification to the testing circuit is not downright enough, and there remain some situations such as unbalance in input resistances, so limitation as to panel size still exists and panels of and above 32 inches cannot be tested; and
2. Symmetrical input mode has to be utilized when carrying out this solution. That is, two input terminals, left and right, are required for the signals. This leads to such problems that, firstly, due to limitation in principles of testing devices, it is impossible to know whether input terminal pads 6 on both sides are all in good contact with the probe pins 5 of the device; secondly, as shown in FIG. 4, due to use of the symmetrical input mode, a beam 8 with a probe pin is required to be added in the middle of a device probe frame 7. Since the distance between the modulator and the glass substrate is only 15 um during the testing, the modulator has to be lifted up once when passing the beam 8, resulting in an increase in tact time and deterioration of manufacture capacity.